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Physical ASIC Design Implementation Engineer

  • Sector: ConSol UK Semiconductors & Embedded Systems
  • Contact: Jamie Jenkins
  • Contact Email: jamie.jenkins@consolpartners.com
  • Duration: 6 months +
  • Start Date: ASAP
  • Location: Leuven
  • Salary: €65 - €70 per hour
  • Expiry Date: 08 May 2024
  • Job Ref: BBBH437807_1707418560

Physical ASIC Design Implementation Engineer

Initial 6 month freelance contract + extensions

Location

  • We provide the flexibility to work both from our office premises (in Leuven, Belgium) and remotely from home. This to maintain a healthy work-life balance while being an integral part of our team and take up this opportunity to undertake this challenging assignment. It is however important that you are residing in Belgium.


We are currently looking for a Physical Implementation engineer for full backend (P&R) projects from netlist-in to GDSII-out flow, for top level chips as well as block level blocks in technologies ranging from N5 to 180nm. This with the full understanding of the complete Cadence Innovus Place & Route flow.

The assignment
In this assignment the selected candidate will be involved in:

  • Setup of full netlist In to GDSII-out P&R flow (libs, derating, low power,..).
  • Place & Route : from floorplanning until postroute.
  • Solve setup/hold/SI/power/... violations.
  • Signoff Timing and Physical/logical verification (LEC, DRC, LVS,...).
  • Discuss constraints/specs with, feedback results to and cooperate with customer.

Required knowledge and skills

  • You have 10 years of experience in physical implementation in advanced nodes (12 - 7nm) and hierarchical designs.
  • You have experience in debugging capabilities
  • You have experience with tcl scripting
  • You can organize your work flexible, and make sure the progress in the project is running smooth
  • To be able to communicate in English is a must, you will also interact with external customers
  • You function well in an international team.