Design for Test (DFT) Engineer - Remote Working

  • Sector: ConSol UK Semiconductors & Embedded Systems
  • Contact: Jamie Jenkins
  • Contact Email: jamie.jenkins@consolpartners.com
  • Duration: 12 months+
  • Start Date: ASAP
  • Location: Germany
  • Salary: €55 - €70 per hour
  • Expiry Date: 26 July 2022
  • Job Ref: BBBH394196_1651060474


Design for Test Engineer
Initial 12 month contract + extensions
Remote Working

Description of Services:
* Provide restrictions and basic conditions to the project.
* Ensure correctness of the deliverables of all assigned tasks and work packages.
* Commitment to achieve the agreed targets: scope, budget, time.
* Strive for synergies with other projects in his field of knowledge.
* Communicate all project relevant information to the Project Owner, Project Manager, e.g. resource/time constraints, risks.
* Constantly available, up-to-date and transparent status of his/her tasks and/or work packages on electronic board.
* Proactively report delays, technical and resource conflicts to Product Owner, Project Manager.
* Proactively highlight and assess risks for the project success in own field of knowledge.
* Assess risks for the execution of a work package user story.
* Perform agreed risk mitigation measures.
* Documentation of results in user story, change request and problem report.

Deliverables and Results:
Implementation of DfT (Design for Test) and BIST (Built-in self-Test) concepts to maximize test coverage while minimizing costs. Insertion of version control systems as a result of our own deliveries. Analyse support requirements for products and develop proposed solutions to optimize test coverage. Work in close coordination with the two major interfaces - chip design and semiconductor manufacturing as well as related areas. Target EDA Tool is Mentor/Siemens Tessent.

Education:
A university degree in Electrical Engineering, Microelectronics, Informatics or a related field.
Requirements:
Digital Design for Test
DFT concept, manufacturing test concepts, memory/logic BIST, scan test architectures, boundary scan,
ATPG, functional pattern development, fault simulation, pattern verification, Design-for-Analysis,
ATE requirements.

Professional Background & Experience:
Up to 8 or more years semiconductor experience gathered through your studies and practical experience.
A basic understanding of typical microcontroller architectures and preferably first impressions of SoC (System-on-Chip) development.

Prior Knowledge:
Design for Test debug capability
Certificates:
Siemens/Mentor Tessent Tools